description and license
open-source tool which enables to visualize component-based systems
together with an engine to automatically synthesize priorities to
ensure system safety. It
developed by (1) Department of Informatics (Unit 6), TU München, (2) fortiss GmbH,
and (3) Verimag Laboratory (CNRS).
The software is released under the
Less General Public License (v3).
- JGraph: Java
for the manipulation of graphs.
- JDD: BDD package
symbolic manipulation of sets of Boolean variables.
- SAT4J: SAT solver
based on Java
Cheng [cheng(at)fortiss(.)org or
cheng.chihhong(at)googlemail(.)com] if you have any problems related to
like to provide bug reports.
(latest update: 2012.10.21)
- Download SW (jar executable on ALL platforms, test cases;
with source code)
- A web page for new
functionalities/bug fixes is
maintained here (20120711).
- (Memory requirement)
If the pre-allocated memory by JVM for VissBIP is not enough, the engine might
halt the synthesis algorithm (on certain platforms). If so, please close the GUI and reexecute
VissBIP with the following instruction in the console "java -jar -Xmx1000m VissBIP.jar" to ensure that appropriate memory is allocated.
- (for reviewers) Please access the following file for the collection of testcases [download]
(including a self-contained instruction).
- Download the source code from [VissBIP_src_20120711.zip].
- The complete
folder is a project which
can be opened by netbeans. To work on the project, simply open netbeans.
- Download an example using VissBIP as a library from [JavaApplication_20120711.zip].
- Use netbeans to open the project. VissBIP.jar is included.
1. Synthesizing local priorities for digital communication modules to avoid deadlock (click on the figure to enlarge).
2. Synthesizing priority-based distributed controllers for multi-core memory protection scheme (click on the figure to enlarge).